Comparative analysis of CMOS adders circuits based on 10 transistors |
| |
Authors: | M. M. Pilipko D. V. Morozov |
| |
Affiliation: | 1. St. Petersburg State Polytechnical University, St. Petersburg, Russia
|
| |
Abstract: | Development of digital signal processing devices has led to appearance of a series of CMOS circuit designs of arithmetic and logic blocks with a small number of transistors. In this paper we suggest a classification of full single-bit CMOS adders, circuits of which consist of 10 transistors. The comparison of main characteristics of adders has been carried out based on the results of circuit simulation for 0.18-micron MOS technology and the most promising implementations have been marked out. |
| |
Keywords: | |
本文献已被 SpringerLink 等数据库收录! |