| 0．18μm直接式数字频率合成器全定制版图设计 |
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| 引用本文： | 张甘英,王丽秀,陈珍海.0．18μm直接式数字频率合成器全定制版图设计[J].电子与封装,2009,9(8):12-15. |
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| 作者姓名： | 张甘英 王丽秀 陈珍海 |
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| 作者单位： | 中国电子科技集团公司第五十八研究所,江苏,无锡,214035 |
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| 摘 要： | 文章采用0．18μm混合信号1P6M1．8W3．3VCMOS工艺，介绍了一种高速直接式数字频率合成器的全定制版图设计。该芯片为数模混合信号IC，电路内部时钟频率达到1GHz。版图设计过程中采用了集成无源金属-绝缘体-金属（MIM）结构电容及深N阱技术，使用了合适的版图布局和电源、地线、时钟网络拓扑结构，最后还对芯片各模块作了版图优化设计。芯片测试结果表明芯片功能全部实现、性能良好，版图设计较好地实现了电路功能。
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| 关 键 词： | 直接式数字频率合成器 版图设计 MIM电容 深N阱 |
Full-custom Layout Design of Direct Digital Frequency Synthesizer in 0.18 μ m CMOS |
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| ZHANG Gan-ying,WANG Li-xiu,CHEN Zhen-hai.Full-custom Layout Design of Direct Digital Frequency Synthesizer in 0.18 μ m CMOS[J].Electronics & Packaging,2009,9(8):12-15. |
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| Authors: | ZHANG Gan-ying WANG Li-xiu CHEN Zhen-hai |
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| Affiliation: | China Electronics Technology Group Corporation No.58th Research Institute;Wuxi 214035;China |
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| Abstract: | The full-custom layout design of a DDFS(Direct Digital Frequency synthesizer)IC is implemented in 0.18μm CMOS 1P6M 1.8V/3.3V process.The chip is a mixed-signal IC,with the clock frequency of 1GHZ.The newest(metal-insulator-metal) MIM capacitors and Deep N-well are used during the layout design.By using appropriate floor planing,clock and power network the layout process is completed.Test results show that the chip's function is fully achieved.The layout design process has successfully realized the function of circuits. |
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| Keywords: | DDFS layout design MIM capacitor deep N-well |
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