Atto-farad measurement and modeling of on-chip coupling capacitance

A first reported method of measuring coupling capacitance (both inter- and intralevel) between any two lines in the presence of any other lines in a very large scale integration (VLSI) chip, to an accuracy of atto-farad range, is discussed. The setup simply requires dc current measurement and the method has been tested for 180 nm and 130 nm technologies. Furthermore, the method can be easily implemented for on-wafer e-test measurement in a fab, to study die-to-die and wafer-to-wafer coupling capacitance variation due to manufacturing process variation. In one process, it has been observed that the coupling capacitance between parallel lines could vary as much as 17%.