基于延迟锁相环和锁频环结构的全数字同步倍频器

针对现有基于PLLs/DLLs的全数字化同步倍频器结构存在的不足，本文提出了基于一种双环结构的全数字同步倍频器。它由延迟锁相环和锁频环共享一个共同的参考时钟信号(FREF)构成，不需要任何模拟组件。它可以采用Verilog-HDL语言设计，可在Altera DE2-70开发板上实现合成，而且可以很容易地适应于不同的FPGA系列以及作为一个集成电路实现，同时也可用于为分布式数字处理系统以及片上系统的片内/片间通信提供时钟参考；实验结果表明，本文所提出的结构相比于现有的结构，能够获得更高频率的输出时钟信号，提供更好的频率分辨率、更好的抖动性能和高倍乘因子。

Delay-locked Loops and Frequency-locked loops Based All-Digital Synchronous Frequency Multiplier

Aiming at the shortages of existing all-digital synchronous multiplier structure based on PLLs/DLLs,an all-digital synchronous multiplier based on a dual-loop architecture is proposed in this paper.It is composed of proposed delay-locked loops and frequency-locked loops that share a common reference clock signal(FREF) and requires no any analog components.The proposed architecture is designed using the Verilog-HDL language and synthesized on the Altera DE2-70 development board,and can be adapted easily for different FPGA families as well as implemented as an integrated circuit.Meanwhile,it can be used in supplying a clock reference for distributed digital processing systems as well as intra/interchip communication in system-on-chip. The experimental results show that the proposed architecture,compared with the existing architectures,can generate output clock signal having a higher frequency,provide better frequency resolution and jitter performance as well as high multiplication factor.