Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology |
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| Authors: | Digeorgia da Silva André I Reis Renato P Ribas |
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| Affiliation: | 1. Institute of Physics, Federal University of Rio Grande do Sul,Av. Bento Gonçalves, 9500, Porto Alegre, 91501-970 RS, Brazil;2. Institute of Informatics, Federal University of Rio Grande do Sul, Av. Bento Gonçalves, 9500, Porto Alegre, 91501-970 RS, Brazil;1. Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil;2. Chaordic Systems, Florianópolis, Brazil;3. Dipartimento di Ingegneria e Scienza dell’Informazione, University of Trento, Italy;4. Istituto di Scienza e Tecnologie dell’Informazione, Consiglio Nazionale delle Ricerche, Pisa, Italy |
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| Abstract: | In digital CMOS circuits, parametric yield improvement may be achieved by reducing the variability of performance and power consumption of individual cell instances. Such improvement of variation robustness can be attained by evaluating parameter variation impact at gate level. Statistical characterization of logic gates are usually obtained by computationally expensive electrical simulations. An efficient gate delay variability estimation method is proposed for variability-aware design. The proposed method has been applied to different topologies (transistor network arrangements) and CMOS gates, and it has been compared to Monte Carlo simulations for data validation, resulting in computation time savings. |
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