Performance Analysis of Microstriplines Interconnect Structure with Novel Guard Trace as Parallel Links for High Speed Dram Interfaces

Wireless communication have progressed so fast in recent years with the increased frequency of operation, faster signal speed, reduced feature size and increased the integration of analog and digital blocks within a constrained space. These made the signal integrity analysis is a challengine task to printed circuit board designers. The signal integrity effects need to be mitigated by the proper design of high speed interconnects. In order to reduce crosstalk and crosstalk induced jitter in high speed parallel links to DRAM interface, a novel parallel microstriplines with U shaped guard trace interconnect structure is proposed. The crosstalk performance of the proposed interconnect structure, it can be implemented in DRAM board and compared with the conventional guard intervening scheme. The proposed structure increased the maximum data rate from 800 Mbps to 3.3 Gbps and reduced CIJ more than 2 ps.