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Design of a C-testable booth multiplier using a realistic fault model
Authors:Jos Van Sas  Chay Nowé  Didier Pollet  Francky Catthood  Paul Vanoostende  Hugo De Man
Affiliation:(1) IMEC Laboratory, Kapeldreef 75, B-3001 Leuven, Belgium;(2) Present address: K.U. Leuven, Leuven, Belgium
Abstract:A Booth multiplier is the most widely used type of multiplier. In this article, the testability issues involved in its design are discussed. In contrast to previous work, the fault model includes not only node stuck-at faults, but also transistor stuck-open and stuck-close faults. Moreover, as a result of adopting a hierarchical testability approach, the designed Booth multiplier turns out to be fully C-testable. To achieve this C-testability, only three additional controllable inputs are required, which results in a negligible area and delay overhead.Currently with Alcatel Bell Telephone.
Keywords:Array multipliers  C-testability  design for testability  fault modelling  test generation
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