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一种全集成高电源抑制比的低压差线性稳压器
引用本文:李志超,刘云涛,旷章曲,陈杰.一种全集成高电源抑制比的低压差线性稳压器[J].半导体学报,2014,35(6):065004-5.
作者姓名:李志超  刘云涛  旷章曲  陈杰
基金项目:国家自然科学基金;创新研究群体科学基金
摘    要:This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR perfor- mance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18μm CMOS technology provided by GSMC (Shanghai, China). Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about -79 dB at low frequency and -40 dB at 1 MHz frequency, while sacrifice of the LDO's active chip-area is only smaller than 0.02 mm2.

关 键 词:CMOS技术  低压差稳压器  电容器  PSR  芯片面积  LDO  输出电压  电源电压

A capacitor-free high PSR CMOS low dropout voltage regulator
Li Zhichao,Liu Yuntao,Kuang Zhangqu and Chen Jie.A capacitor-free high PSR CMOS low dropout voltage regulator[J].Chinese Journal of Semiconductors,2014,35(6):065004-5.
Authors:Li Zhichao  Liu Yuntao  Kuang Zhangqu and Chen Jie
Affiliation:Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;Superpix Micro Technology Co. Ltd, Beijing 100085, China;Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Abstract:CMOS low dropout regulator power supply rejection capacitor-free
Keywords:CMOS  low dropout regulator  power supply rejection  capacitor-free
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