高速异步FIFO的设计和实现

本文介绍了一种新型异步FIFO的设计和ASIC实现,与传统的格雷码作异步FIFO指针的方法不同,该FIFO实现方案采用了一种移位码,在避免了亚稳态出现的同时缩短了关键路径,提高了工作频率。本设计采用Verilog硬件描述语言实现,具有良好的可移植性和设计灵活性。最后,给出了系统的综合实现结果。

Design and Implementation of High-Speed Asynchronous FIFO

A high-speed asynchronous FIFO design and its ASIC implementation are introduced in this paper. This implementation uses a novel shift address coding instead of the traditional Gray code. This shift coding solves the meta-stable problem which usually happens in asynchronous circuits and shortens the critical path. It can run faster than the Gray code FIFO. The design uses the Verilog hardware description language, and has good portability and design flexibility. Finally, a synthesized timing result is given...