Au–Sn flip-chip solder bump for microelectronic and optoelectronic applications

As an alternative to the time-consuming solder pre-forms and pastes currently used, a co-electroplating method of eutectic Au–Sn alloy was used in this study. Using a co-electroplating process, it was possible to plate the Au–Sn solder directly onto a wafer at or near the eutectic composition from a single solution. Two distinct phases, Au₅Sn (ζ-phase) and AuSn (δ-phase), were deposited at a composition of 30 at.%Sn. The Au–Sn flip-chip joints were formed at 300 and 400°C without using any flux. In the case where the samples were reflowed at 300°C, only an (Au,Ni)₃Sn₂ IMC layer formed at the interface between the Au–Sn solder and Ni UBM. On the other hand, two IMC layers, (Au,Ni)₃Sn₂ and (Au,Ni)₃Sn, were found at the interfaces of the samples reflowed at 400°C. As the reflow time increased, the thickness of the (Au,Ni)₃Sn₂ and (Au,Ni)₃Sn IMC layers formed at the interface increased and the eutectic lamellae in the bulk solder coarsened.