| 10.5GHz1:2静态分频器设计与实现 |
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| 引用本文： | 张敏,张有涛,陈新宇.10.5GHz1:2静态分频器设计与实现[J].固体电子学研究与进展,2008,28(4). |
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| 作者姓名： | 张敏 张有涛 陈新宇 |
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| 作者单位： | 南京电子器件研究所,南京,210016 |
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| 摘 要： | 采用0.18μm CMOS工艺设计并实现了1∶2静态分频器。设计中为达到高速率和高灵敏度,对传统的SCFL结构D触发器进行了拓扑及版图优化。测试结果表明,电源电压为1.8V时,该分频器最高工作频率高于10.5GHz,最低工作频率低于2.5MHz(受测试条件限制),输入信号0dBm时的工作频率范围为2.5MHz～9.4GHz,芯片核心功耗9mW,核心面积50μm×53μm。
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| 关 键 词： | 分频器 触发器 互补金属氧化物半导体 集成电路 |
Design and Realization of 10.5 GHz 1:2 Static Frequency Divider |
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| ZHANG Min,ZHANG Youtao,CHEN Xinyu.Design and Realization of 10.5 GHz 1:2 Static Frequency Divider[J].Research & Progress of Solid State Electronics,2008,28(4). |
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| Authors: | ZHANG Min ZHANG Youtao CHEN Xinyu |
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| Affiliation: | ZHANG Min ZHANG Youtao CHEN Xinyu (Nanjing Electronic Devices Institution,Nanjing,210016,CHN) |
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| Abstract: | An 1∶2 static frequency divider is realized in 0.18 μm standard CMOS technology. By optimizing the topology and layout of the traditional SCFL D-flip-flop,high speed and high sensitivity are achieved. Test results show that the maximum operation frequency is higher than 10.5 GHz and the minimum operation frequency is lower than 2.5 MHz,under the existed equipment condition. And the operation frequency range at 0 dBm input signal is 2.5 MHz～9.4 GHz. The core circuit consumes 9 mW from a 1.8 V supply and occupies 50 μm×53 μm. |
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| Keywords: | frequency divider flip-flop CMOS IC |
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