A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter(ADC)with a low over-sampling rate is presented.The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC,and operates at a low 8X oversampling rate.The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique.The ADC operates at a 4MHz clock rate and dissipates 300mW at a 5V/3V analog/digital power supply.It is developed i...