Generating tests for delay faults in nonscan circuits |
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Authors: | Agrawal P Agrawal VD Seth SC |
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Affiliation: | AT&T Bell Labs., Murray Hill, NJ; |
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Abstract: | A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing |
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