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A 21-mW 8-b 125-MSample/s ADC in 0.09-mm/sup 2/ 0.13-/spl mu/m CMOS |
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| Authors: | Mulder J. Ward C.M. Chi-Hung Lin Kruse D. Westra J.R. Lugthart M. Arslan E. van de Plassche R.J. Bult K. van der Goes F.M.L. |
| Affiliation: | Broadcom Netherlands, Bunnik, Netherlands; |
| Abstract: | This paper presents an 8-b two-step subranging analog-to-digital (ADC) using interpolation, averaging, offset compensation, and pipelining techniques to accomplish an effective number of bits of 7.6 b at 125 MSample/s. The 0.13-/spl mu/m CMOS ADC occupies 0.09 mm/sup 2/ and consumes 21 mW. |
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