多总线平台一体化测试系统时钟同步和触发设计

随着现代被测对象复杂性的增加以及单一接口形式测试总线产品种类的限制,大多情况下必须要构建多总线平台一体化测试系统;然而不同接口形式的测试设备时钟同步和触发机制不同,多总线平台一体化过程中时钟同步和触发的统一是必须要考虑的问题;在提出了基于硬线的方式、基于PTP的方式以及混合方式三种时钟同步和触发设计的同时,以在研项目硬件设备为平台,对其性能进行了测试;结果显示,方案不同同步精度不同,基于硬线和PTP的方式最大同步偏差分别为50ns和523ns,可适用于不同的测试场景.

Clock Synchronization and Trigger Design of Integrated Test System Based on Multiple Bus Platform

With the increasing complexity of modern UUT and the confinement of unique interface test bus product types,in most cases,the integrated test system based on multiple bus system must be created.However,because test instruments and devices of different interface have different clock synchronization and trigger mechanism,in the process of integrating multiple bus platform,the unification of clock synchronization and trigger is a problem that must be considered.This paper introduce three methods of clock synch...