基于VHDL语言的数字电路测试码自动生成

本文提出了一种新的基于VHDL语言的组合数字电路测试码自动生成方法。在VHDL语言描述组合数字电路的基础上，建一VHDL语言的编译器，并输入为描述被测电路的VHDL语言，输出结果为描述被测电路功能的一系列逻辑表达式。针对这些逻辑表达式，本文详细地介绍了一种能直接产生电路测试码的算法。

Automatic Generation of Test Patterns for Digital ICS Based on VHDL Language

The paper proposes a mew method for testing combinational digital circuit which is based on the VHDL language. At first, provided that a VHDL language program describes the combinational digital circuit which should be tested,we can set up a compiler in which the input is the VHDL language and the output is a series of logic expressions describing the function of the tested circuit. At last,we will particularly introduce a method directly generating the digital circuit test pattern which is based on these logic expressions.