| LDPC码全并行译码器的设计与实现 |
| |
| 引用本文： | 王建新,向国菊.LDPC码全并行译码器的设计与实现[J].电路与系统学报,2009,14(5). |
| |
| 作者姓名： | 王建新 向国菊 |
| |
| 作者单位： | 南京理工大学,电子工程与光电技术学院,江苏,南京,210094 |
| |
| 摘 要： | 本论文用可编程逻辑器件(FPGA)实现了一种低密度奇偶校验码(LDPC)的编译码算法.采用基于Q矩阵LDPC码构造方法,设计了具有线性复杂度的编码器. 基于软判决译码规则,采用全并行译码结构实现了码率为1/2、码长为40比特的准规则LDPC码译码器,并且通过了仿真测试.该译码器复杂度与码长成线性关系,与Turbo码相比更易于硬件实现,并能达到更高的传输速率.
|
| 关 键 词： | LDPC码 编码器 软判决译码 全并行译码器 |
Design and implementation of a full parallel LDPC decoder |
| |
| WANG Jian-xin,XIANG Guo-ju.Design and implementation of a full parallel LDPC decoder[J].Journal of Circuits and Systems,2009,14(5). |
| |
| Authors: | WANG Jian-xin XIANG Guo-ju |
| |
| Affiliation: | WANG Jian-xin,XIANG Guo-ju(Nanjing University of Science , Technology,Nanjing 210094,China) |
| |
| Abstract: | An encoder/decoder for the low density parity codes(LDPC) with FPGA techniques is implemented in this paper.An LDPC encoder is designed based on the Q-matrix construction method.The resulting encoder has the linear complexity with code block length.Based on soft-decision algorithm,a parallel decoder of LDPC code(rate 1/2,block length 40 bits) is realized.The whole design is verified through computer simulations.This decoder has the advantage of linear complexity with block length.It can be realized more eas... |
| |
| Keywords: | LDPC encoder soft-decision decoding parallel decoder |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
|
