一种DSP用数模混合型锁相环设计

提出了一种用于DSP的高性能低噪声高速电荷泵锁相环电路。其鉴频鉴相器模块具有高速、无死区等特点;电荷泵模块在提高开关速度的基础上改进了拓扑结构,使充放电电流的路径深度相同,更好地实现了匹配。为了达到宽调谐范围的目的,电荷泵模块采用1.8V电源电压,而压控振荡器模块采用3.3V,这样可充分利用电荷泵的输出电压范围实现宽调谐。电路设计基于0.18μm1P6MCMOS工艺,结果表明,锁相环电路功耗为34mW,中心频率100MHz,频率输出范围50MHz～400MHz,各项性能满足设计指标要求,并使芯片噪声、速度和功耗最优。各模块电路可应用于其他相应的功能电路,对相关领域的设计具有一定的参考意义。

A Digital-analogy Mixed PLL Design for DSP

A high speed, low power phase-locked loop（PLL） is designed for DSE A pre-charge mode was used in phase/frequency detector to realize high speed and dead zone free, etc.The topology of the circuit was also enhanced to equalize the depths of charge and discharge currents,which improved the circuit matching.In order to expand the tuning range of the PLL,a 1.8V power supply was used in the charge pump module,while a 3.3V power supply was used for VCO module.This circuit was implemented in a 0.18/a m 1P6M CMOS technology, results showed that the PLL operated in the frequency range between 50MHz and 400MHz. The research not only satisfied the needs of present work, but also supplies a worthful theory for PLL design in future.