应用于高速串行接口的低噪声时钟发生器

设计了一种应用于28 Gbit/s高速串行接口的低噪声时钟发生器,包括全差分电荷泵、差分环路滤波器、差分压控振荡器。为了降低相位噪声,采用全差分结构来降低共模噪声和电流失配。为了进一步降低小数分频器引入的噪声,提出一种基于计数器的分频器。为了保证时钟发生器在各种工艺和温度偏差下均能自动锁定,设计了自适应调谐电容电路。采用65 nm CMOS工艺进行设计,芯片面积为0.36 mm²,整体功耗为36 mW。后仿真结果表明,该时钟发生器在14 GHz 锁定后的相位噪声是-113 dBc@1 MHz,压控振荡器的调谐范围是12.8~15.0 GHz,自动锁定电路能在全调谐范围内对电路进行自动调整和锁定。

A Low Noise Clock Generator for High Speed Serial Interface

A low noise clock generator for 28 Gbit/s high speed serial interface was designed. It consisted of fully differential charge pumps, differential loop filters, and differential voltage controlled oscillators. To improve the phase noise performance, a fully differential architecture was used to reduce the common mode noise and current mismatch. To further reduce the noise introduced by the fractional divider, a counter-based fractional divider circuit was proposed. Finally, in order to ensure that the clock generator could be automatically locked under various process and temperature deviations, an adaptive tuning capacitor circuit was designed. The clock generator was designed in a 65 nm CMOS process with an overall chip area of 0.36 mm² and a power consumption of 36 mW. The post-simulation results showed that the phase noise of the proposed circuit was -113 dBc @1 MHz after locking at 14 GHz, and the tuning range of the VCO was 12.8-15.0 GHz. The automatic locking circuit could ensure automatic adjustment and locking in the full tuning range.