Synergistic design of an application-oriented sparse directory on many-core embedded systems |
| |
| Affiliation: | 1. School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China;2. Xi’an Jiaotong Liverpool University, Suzhou, China;1. Department of Information Engineering and Computer Science, Feng Chia University, Taichung 407, Taiwan, ROC;2. Department of Industrial Engineering and Management, National Yunlin University of Science and Technology, Yunlin 640, Taiwan, ROC;1. College of Computer and Information Engineering, Xiamen University of Technology, China;2. National Laboratory for Parallel and Distributed Processing, National University of Defensive Technology, China;3. Graduate School of Engineering, Nagoya University, Japan;4. Graduate School of Information Science, Nagoya University, Japan;5. College of Computer Science and Electronic Engineering, Hunan University, China;6. School of Computer and Software, Nanjing University of Information Science and Technology, China;1. Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan;2. Department of Computer Science and Information Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan;1. Department of Computer Science, Yonsei University, Korea;2. Department of Computer Engineering, Hongik University, Korea |
| |
| Abstract: | As many-core embedded systems are evolving from single-memory based designs to systems-on-a-chip running on an on-chip network, implementing a cache coherence mechanism in large-scale many-core embedded systems turns out to be a technical challenge. However, existing coherence mechanisms are difficult to scale beyond tens of cores, which require either excessive area or energy, complex hierarchical protocols, or inexact representations of sharer sets. In this paper, we present a hardware-software synergistic design of a cache coherence mechanism by considering OS-level application allocation and hardware-level coherence operations. The proposed application-oriented sparse directory (AoSD) cooperates with a contiguous allocation algorithm to isolate cache coherence traffic and thereby reduce interferences among applications. The proposed micro-architecture of sharer set representations is area-efficient; moreover, it can also be configured dynamically to track a flexible and exact sharer set. We verify our design by analyzing memory requirements of different cache organizations and implementing our design on a popular simulator Graphite to evaluate cache coherence traffic improvement. The results show that our design is both area-efficient and efficient with improvements in memory network performance by 11.74%–28.72%. It is also indicated that our design is feasible to scale up to work well in thousands-of-cores embedded systems. |
| |
| Keywords: | |
| 本文献已被 ScienceDirect 等数据库收录！ |
|
