| 基于FPGA的高速计数器设计 |
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| 引用本文： | 何永泰,肖丽仙.基于FPGA的高速计数器设计[J].电气应用,2006,25(4):140-142,133. |
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| 作者姓名： | 何永泰 肖丽仙 |
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| 作者单位： | 1. 楚雄师范学院物理与电子科学系,675000
2. 楚雄应用技术学院,675000 |
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| 摘 要： | 为了提高工业控制器中高速计数器的计数频率和扩展计数模式,介绍一种利用FPGA,通过VHDL语言设计的高速计数器,有15种工作模式,计数频率可达100kHz以上。同时介绍了高速计数器的设计原理,提供了高速计数器与微处理器的接口实例。
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| 关 键 词： | 高速计数器 现场可编程逻辑阵列 VHDL语言 |
| 修稿时间： | 2005年6月16日 |
Besign of High Speed Counter Based on FPGA |
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| He Yongtai.Besign of High Speed Counter Based on FPGA[J].Electrotechnical Application,2006,25(4):140-142,133. |
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| Authors: | He Yongtai |
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| Affiliation: | Chuxiong Normal University |
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| Abstract: | Improving count frequency and model of high speed counter, high speed counter is designed by FPGA and VHDL language. The high speed cou nter has 15 kind count model and over 100kHz count frequency. Designed theory of high speed counter is introduced. An application example with MCU is given. The high speed counter has application value in the technical controller. |
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| Keywords: | (HSC) (FPGA) |
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