基于半随机矩阵的LDPC编码器的Verilog HDL设计

低密度奇偶校验码(Low-Density-Parity-Checkcodes,LDPC码)是第四代通信系统强有力的竞争者,是一种逼近香农限的线性分组码,译码的复杂度较低;其直接编码运算量较大,通常具有码长的二次方复杂度．介绍了如何构造线性的编码,以降低LDPC码的编码复杂度;研究并设计了用大规模集成电路去实现一个LDPC码的编码．以(6,2,3)码为例,采用基于半随机校验矩阵的编码方法,以控制编码运算量为线性复杂度,并在QuartusII5．0软件平台上采用基于CPLD的Veril- ogHDL语言编程仿真实现了编码的过程,给出了编码的结构图和仿真波形,为LDPC码的硬件实现和实际应用提供了依据．

Design of Encoder for Low Density Parity Check Codes in Verilog HDL based on Half Random Matrix

As a powerful competitor in the 4th generation of mobile communication system, Low-Density-Parity-Check-Codes is a kind of linear group codes which can be near the Shannon limit, the complexity of decoding is low, but the amount of operations about directly encoding Low Density Parity Check Codes (LDPC) is large, the complexity of encoding is the square of the length of codeword. In order to simplify the encoding operation, how to structure linear code is introduced, and how to realize the encoding device is studied by using large integrate circuit. This article takes the code (6,2,3) as an example,uses encoding method on half random parity check matrix so as to control the amount of operations to be linear, and we have designed the effective coding algorithm based on CPLD in VHDL language by QuartusII5.0 software and presented their simulating waveforms. It can be supplied to the realizing of hardware and applicated to pratice.