| 一种硬感知器的结构设计与EPGA实现 |
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| 引用本文： | 谢云,章云,刘冰茹,易波.一种硬感知器的结构设计与EPGA实现[J].广东工业大学学报,2003,20(3):46-49,53. |
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| 作者姓名： | 谢云 章云 刘冰茹 易波 |
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| 作者单位： | 广东工业大学,自动化学院,广东,广州,510090 |
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| 摘 要： | 分析了单个神经元神经网络(即感知器)的结构特征；介绍了自顶向下的FPGA的设计方法，并在QUARTUS^TM Ⅱ软件平台上实现了单个神经元的硬件神经网络．
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| 关 键 词： | 神经网络 感知器 FPGA VHDL 自顶向下 |
| 文章编号： | 1007-7162(2003)03-0046-04 |
Structural Design of a Hard-wired Sense Part and Its Realization with FPGA |
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| XIE Yun,ZHANG Yun,LIU Bing-ru,YI Bo Faculty of Automation,Guangdong University of Technology,Guangzhou ,China.Structural Design of a Hard-wired Sense Part and Its Realization with FPGA[J].Journal of Guangdong University of Technology,2003,20(3):46-49,53. |
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| Authors: | XIE Yun ZHANG Yun LIU Bing-ru YI Bo Faculty of Automation Guangdong University of Technology Guangzhou China |
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| Affiliation: | XIE Yun,ZHANG Yun,LIU Bing-ru,YI Bo Faculty of Automation,Guangdong University of Technology,Guangzhou 510090,China |
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| Abstract: | |
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| Keywords: | neural network sense part FPGA VHDL Top-Down |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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