MIMO实验系统中的数据缓冲应用研究

研究了基于FPGA控制的SDRAM Module在移动通信的MIMO技术实验系统中的应用,主要介绍了MIMO实验系统硬件平台、SDRAM的特点及其控制器软核的VHDL设计,以及USB2.0方式的数据传输。通过对页面读写、突发读写、集总和定时刷新等工作方式的灵活运用,很好地解决了MIMO无线通信中的海量数据高速缓冲问题。经MIMO实验系统验证表明,SDRAM控制器的数据缓冲方案高效可行,适用性突出。

Research on the Application Solution for Data Buffer in MIMO Experimental Systems

The wireless communication system is up against various engineering challenges. For both the transmitted and the received data processing, fast-access memories with large capacity are required in experimentation systems with Multiple-Input & Multiple-Output technique. SDRAM is a kind of random access memory with large-capacity and high-speed, but many Microprogrammed Control Units or normal Digital Signal Processors cannot directly interface with SDRAM due to the differences between control signals. Based on FPGA(field programmable gate array), a design method of SDRAM controller with USB interface to computer is proposed. Large-capacity data access is implemented at high speed by the controller circuit, which is working effectively in our MIMO experimentation system.