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新型全数字三相SPWM信号产生芯片的设计与实现
引用本文:高勇,余宁梅,陈利杰,唐善强. 新型全数字三相SPWM信号产生芯片的设计与实现[J]. 半导体学报, 2006, 27(1): 126-131
作者姓名:高勇  余宁梅  陈利杰  唐善强
作者单位:西安理工大学电子工程系,西安,710048
摘    要:
针对电力电子领域的需要,自行研制了一种新型三相正弦脉宽调制信号产生芯片.该芯片采用了改进的直接数字频率合成算法、流水线结构与ROM分时复用技术,保证了芯片的高性能和速度,节省了芯片面积.芯片系统时钟可达24MHz,输出信号的范围为DC到4kHz,精度为65536级,控制功能齐全.采用0.35μm COMS工艺流片,测试结果显示芯片达到设计指标.

关 键 词:数字频率合成  正弦脉宽调制  正弦波查找表  COMS
收稿时间:2015-08-20

Design and Implementation of a Novel Chip for Full Digital Three-Phase SPWM Signal Generation
Gao Yong, Yu Ningmei, Chen Lijie, Tang Shanqiang. Design and Implementation of a Novel Chip for Full Digital Three-Phase SPWM Signal Generation[J]. Journal of Semiconductors, 2006, In Press. Gao Y, Yu N M, Chen L J, Tang S Q. Design and Implementation of a Novel Chip for Full Digital Three-Phase SPWM Signal Generation[J]. Chin. J. Semicond., 2006, 27(1): 126.Export: BibTex EndNote
Authors:Gao Yong  Yu Ningmei  Chen Lijie  Tang Shanqiang
Affiliation:Department of Electronic Engineering,Xi’an University of Technology,Xi’an 710048,China;Department of Electronic Engineering,Xi’an University of Technology,Xi’an 710048,China;Department of Electronic Engineering,Xi’an University of Technology,Xi’an 710048,China;Department of Electronic Engineering,Xi’an University of Technology,Xi’an 710048,China
Abstract:
A novel full digital three-phase sinusoidal pulse width modulation (SPWM) signal generation chip is presented for power electronics.A modified direct digital frequency synthesis(DDS),pipelined structure,and time-sharing ROM are adopted in the chip,for saving chip area and ensuring high performance and speed.The system clock is set at 24MHz,the output signals defined in 65536 equal steps cover a bandwidth from DC to 4kHz,and the multifunction is designed for control.The chip is fabricated by using charted 0.35μm COMS technology.The test results show that the chip achieves the design specification
Keywords:DDS   SPWM   look-up table   COMS
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