亚70nm CMOS工艺低漏电流、高噪声容限的低功耗多输入多米诺或门的设计

提出了两种新的电路技术,在降低多输入多米诺"或门"的动态功耗的同时减小了漏电流,并提高了电路的噪声容限.采用新的电路技术设计了八输入多米诺"或门"并基于45nm BSIM4 SPICE 模型对其进行了模拟.模拟结果表明,设计的两种新多米诺电路在同样的噪声容限下有效地降低了动态功耗,减小了总的漏电流,同时提高了工作速度.与双阈值多米诺电路相比,设计的两种电路动态功耗分别降低了8.8%和11.8%,电路速度分别提高了9.5%和13.7%,同时总的漏电流分别降低了80.8%和82.4%.基于模拟结果,也分析了双阈值多米诺电路中求值点的不同逻辑状态对总的漏电流的影响.

Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies

Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed.Eight-input OR gate circuits constructed with these techniques are simulated using 45nm BSIM4 SPICE models in HSPICE.The simulation results show that the proposed circuits effectively lower the active power,reduce the total leakage current,and enhance speed under similar noise immunity conditions.The active power of the two proposed circuits can be reduced by up to 8.8% and 11.8% while enhancing the speed by 9.5% and 13.7% as compared to dual Vt domino OR gates with no gating stage.At the same time,the total leakage currents are also reduced by up to 80.8% and 82.4%,respectively.Based on the simulation results,the state of the evaluation node is also discussed to reduce the total leakage currents of dual Vt dominos.