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| 超大规模集成电路的可制造性设计 | |
| 引用本文： | 郭琦,李惠军. 超大规模集成电路的可制造性设计[J]. 微纳电子技术, 2005, 42(9): 435-439 |
| 作者姓名： | 郭琦 李惠军 |
| 作者单位： | 山东大学孟堯微电子研发中心,济南,250100 |
| 摘 要： | 以Synopsys推出的TCAD软件TSUPREM-Ⅳ和Medici为蓝本,结合100nm栅长PMOSFET的可制造性联机仿真与优化实例,阐述了超大规模集成电路DFM阶段所进行的工艺级、器件物理特性级优化及工艺参数的提取。 |
| 关 键 词： | 超大规模集成电路 深亚微米 可制造性设计 |
| 文章编号： | 1671-4776(2005)09-0435-05 |
| 修稿时间： | 2005-02-17 |
Design for Manufacturability of VLSI |
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| GUO Qi,LI Hui-jun. Design for Manufacturability of VLSI[J]. Micronanoelectronic Technology, 2005, 42(9): 435-439 | |
| Authors: | GUO Qi LI Hui-jun |
| Affiliation: | GUO Qi,LI Hui-jun Mengyao Microelectronics Research and Development Centre,Shandong University,Ji'nan 250100,China |
| Abstract: | With the Synopsys TCAD design tools including TSUPREM-Ⅳ and Medici, the process and device simulation are introduced by extracting and comparing the characteristics of the 100 nm gate length PMOSFET transistors with different process conditions and parameters. |
| Keywords: | very large scale integrated circuit (VLSI) deep submicron (DSM) design for manufacturability (DFM) |
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