Modelling of scaled-down MOS transistors |
| |
Authors: | F.M. Klaassen W.C.J. de Groot |
| |
Affiliation: | Philips Research Laboratories, Eindhoven, The Netherlands |
| |
Abstract: | Short-channel MOS transistors exhibit a drain current saturation behaviour different from that of longer channels. By comparing measured and calculated characteristics it is shown that the current increase can be successfully interpreted as a threshold voltage shift proportional to the drain voltage. A circuit model is derived which takes into account the above effect and includes an improved saturation mechanism. Compared with existing models the present one yields smaller deviations between measured and calculated characteristics and does not need non-physical parameters values. |
| |
Keywords: | |
本文献已被 ScienceDirect 等数据库收录! |