Reduced processing element architecture for parallel local image processing |
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| Authors: | Po‐Ning Chen Yung‐Sheng Chen Wen‐Using Hsu |
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| Affiliation: | 1. Institute of Electrical Engineering , National Tsing Hua University , Hsinchu, Taiwan, 30043, R.O.C.;2. Institute of Electrical Engineering , National Tsing Hua University , Hsinchu, Taiwan, 30043, R.O.C.;3. Institute of Information Science , Academia Sinica , Taipei, Taiwan, R.O.C. |
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| Abstract: | Abstract The object of this paper is to propose new architecture which can reduce the number of processing elements for parallel local image processing under the premise of real‐time performance. For large‐sized local image processing, this architecture will save much space as it is suitable for being designed into VLSI chip. For example, the traditional parallel architecture will use 9 PEs for a 3×3 convolution, while the Reduced Processing Element Architecture (RPEA) only requires 2 PEs to achieve the real‐time performance. |
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| Keywords: | image processing local operation convolution |
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