Lower-error and area-efficient antilogarithmic converters with bit-correction schemes

In this article, we have proposed fast lower-error and area-efficient antilogarithmic converters. By employing new approximation schemes with two-region shift-and-add operations, our proposed converters can perform high-speed conversions from logarithmic numbers to binary numbers. Synthesis results show that our proposed converters can achieve time savings of over 32.5% and can save 42.3% of the area used compared with previously proposed methods. In addition, the percent error ranges for various logarithmic number system (LNS)-based operations used by our proposed logarithmic processor are lower than those of previous methods. Our proposed converters can be applied to LNS-based processors to ease the tremendous computation overhead and boost the performance.