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An FPGA implementation of a neural optimization of block truncation coding for image/video compression |
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| Authors: | Sherif Saif Hazem M Abbas Salwa M Nassar Abdelmonem A Wahdan |
| Affiliation: | aMentor Graphics Corp., 51 Beirut Street, Cairo 11341, Egypt bComputers and Systems Department, Electronics Research Institute (ERI), Giza, Egypt cDepartment Computer and Systems Engineering, Ain Shams University, Cairo, Egypt |
| Abstract: | This paper presents a Field Programmable Gate Array (FPGA) implementation for image/video compression using an improved block truncation coding (BTC) image compression technique. The improvement is achieved by employing a Hopfield neural network (HNN) to calculate a cost function upon which a block is classified as either a high- or a low-detail block. Accordingly, different blocks are coded with different bit rates and thus resulting in better compression ratios. The paper formulates the utilization of HNN within the BTC algorithm in such a way that a viable FPGA implementation is produced. The implementation exploits the inherent parallelism of the BTC/HNN algorithm to provide efficient algorithm-to-architecture mapping. The Xilinx VirtexE BTC implementation has shown to provide a processing speed of about 1.113 × 106 of pixels per second with a compression ratio which varies between 1.25 and 2 bits/pixel, according to the image nature. |
| Keywords: | Field programmable gate arrays Block truncation coding Hopfield neural networks Image/video compression |
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