| 取样示波器主控单元CPLD |
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| 引用本文： | 何先忠,潘仲英,林萍实. 取样示波器主控单元CPLD[J]. 电子测量技术, 2003, 0(5): 3-4 |
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| 作者姓名： | 何先忠 潘仲英 林萍实 |
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| 作者单位： | 北京航空航天大学 |
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| 摘 要： | 提出一种取样示波器主控单元的设计方法和硬件软件化的设计思路，用Verilog硬件描述语言进行设计。用EDA工具进行综合和仿真，在单片CPLD上实现了取样示波器主控单元电路。
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| 关 键 词： | 取样示波器 CPLD Verilog硬件描述语言 EDA工具 电路设计 工作原理 |
Implementation of a Controlling Part for Sampling Oscilloscope by CPLD |
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| He Xianzhong Pan Zhongying Lin Pinshi. Implementation of a Controlling Part for Sampling Oscilloscope by CPLD[J]. Electronic Measurement Technology, 2003, 0(5): 3-4 |
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| Authors: | He Xianzhong Pan Zhongying Lin Pinshi |
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| Affiliation: | He Xianzhong Pan Zhongying Lin Pinshi |
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| Abstract: | A method for designing Controlling Part of Sampling Oscilloscope by using EDA technology is presented. By Verilog HDL programming, synthesizing, simulating, the controlling function of Sampling Oscilloscope in a single CPLD chip is implemented. |
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| Keywords: | Sampling Ostillcscope Verilog HDL CPLD |
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