A novel pulse swallow based frequency divider circuit for a phase-locked loops

In this paper, an analysis of the memory effect in two amplifier-shared switched-capacitor integrators for a discrete-time sigma-delta (\(\varSigma \varDelta\)) modulator is presented. Interaction between the integrators is modeled by feeding an integrator output voltage to another integrator input and vice versa and multiplying by a coefficient depending on DC gain and input parasitic capacitance of the opamp. The model is applied to a second-order \(\varSigma \varDelta\) modulator to analyze how signal and noise transfer functions are altered. The analysis reveals that the magnitude response of the signal transfer function is minimally affected in the low-frequency signal band, whereas that of the noise transfer function can be increased significantly in the signal band, degrading the effectiveness of noise shaping. In relation to the parasitic capacitance at the opamp input, the DC gain required of the opamp is derived quantitatively for a given degradation of modulator dynamic range with respect to different oversampling ratios. Considering leaky integration, which is also caused by the finite opamp DC gain, the DC gain requirement imposed by the memory effect is proved to be more severe than that by leaky integration. Macromodel-based circuit simulation results confirm the accuracy of the proposed model and equations.