A comprehensive study of various etch processes for the removal of silicide-block-film in submicron CMOS technologies

The removal of silicide-block-film is crucial for device stability, reliability and subsequent silicide formation. In this paper, various silicide block etch processes, i.e. dry and wet etch, were studied and compared. Possible plasma charging damage during dry etch might caused unstable PMOS threshold voltage (V_th) during H₂ annealing. The impacts of the plasma-process-induced-damage (PPID), including V_th shift, its channel length dependency, and its thermal stability were investigated. The PPID can be eliminated by reducing bias power and magnetic field, while sacrificing etch rate (ER) and equipment throughput. The main advantages of wet etch are immunity from PPID, and little surface damage resulting in uniform silicide formation. However, it also has disadvantages: buffered oxide etchant (BOE) leads to the appearance of poly pinholes, and diluted hydrofluoric acid (DHF) peels the photoresist (PR) off. Therefore, wet etch can only be used in the situation of short etching time such as the combined dry and wet etch.