1.2 nm capacitance equivalent thickness gate stacks on Si-passivated GaAs

Experiments to increase the specific capacitance of MOS capacitors consisting of HfO₂ on a passivating interfacial layer (IL) of amorphous Si (a-Si) on GaAs are described. XPS analysis of the layers and electrical measurements on the capacitors are combined to study the evolution of the gate stack during deposition and subsequent heat treatments. It is shown that oxidation of the a-Si IL is a major factor in preventing the attainment of a scaled capacitance equivalent thickness (CET). By controlling the deposition of the layers, the gate metal and the heat treatments, a highly scaled gate stack with a CET of 1.2 nm and a leakage reduction of more than 4 orders of magnitude with respect to SiO₂/Si was realized.