Design considerations for improving low-temperature noise performance of silicon JFET's |
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| Authors: | J.W. Haslett E.J.M. Kendall F.J. Scholz |
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| Affiliation: | Department of Electrical Engineering, The University of Calgary, Alberta, Canada |
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| Abstract: | A study of the effects of channel doping and device geometry variations on the operation of silicon JFET's has been carried out in an attempt to optimize the noise performance of such devices at low temperatures. In order to obtain optimum performance at temperatures below 125°K, low values of channel doping and large channel dimensions must be used. The high frequency electrical performance of such devices is poor because of larger parasitic capacitances. |
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