An efficient bit-serial FIR filter architecture

A new bit-serial architecture for implementation of high order FIR filters is introduced, as well as example FPGA and CMOS realizations. This structure exploits the simplicity of coefficients that consist of two power-of-two terms to yield efficient implementations. Quantization effects are discussed and a simple block scaling method for reducing rounding and truncation noise in high order filters is also presented.This research is supported by the Office of Naval Research under Grant N00014-89-J1327, NSF Grant ECS87-13598, by an AT&T Bell Laboratories Graduate Fellowship, and by University of Kansas General Research allocation 3775-20-0038. Portions of this work were presented at ICASSP-90 in Albuquerque, New Mexico.