二元域大型稀疏矩阵向量乘的FPGA设计与实现

作为Wiedemannn算法的核心部分,稀疏矩阵向量乘是求解二元域上大型稀疏线性方程组的主要步骤。提出了一种基于FPGA的二元域大型稀疏矩阵向量乘的环网硬件系统架构,为解决Wiedemannn算法重复计算稀疏矩阵向量乘,提出了新的并行计算结构。实验分析表明,提出的架构提高了Wiedemannn算法中稀疏矩阵向量乘的并行性,同时充分利用了FPGA的片内存储器和吉比特收发器,与目前性能最好的部分可重构计算PR模型相比,实现了2.65倍的加速性能。

Design and implementation of large sparse matrix vector multiplication on FPGA over GF(2)

As the kernel part of Wiedemannn algorithm, the sparse matrix vector multiplication (SpMV) is the main step for solving large sparse system of linear equations. In order to solve the problem of repeated SpMV computation, we propose a torus network architecture for large spare matrix vector multiplication based on FPGA over GF(2). The implementation simplifies the design of the algorithm, improves the algorithm parallelism and the utilization of Block RAM on chip and GTX, and obtains a speedup of 2.65 times in comparison with the partial reconfiguration design.