一种多级无缓存高阶路由器的设计与实现

随着高性能网络规模的增加,高阶路由器结构设计成为高性能计算研究的重点和热点。使用高阶路由器,网络能实现更低的报文传输延迟、网络功耗和网络构建成本,同时高阶路由器的应用还可以提高网络可靠性。高性能路由器的阶数不断提高,仅靠扩展单级crossbar交换结构的阶数使路由器内部的连线资源急速增长,交叉开关的实现代价将不可接受,这就需要为高阶路由器设计新型的交换结构。近十年来,出现了以YARC为代表的经典结构化设计以及"network within a network"等新型设计方法,未来的研究重点是解决高阶路由器结构设计中遇到的缓存、仲裁和扩展性等各种问题。鉴于此,实现了一种多级无缓存高阶路由器,这种高阶路由器内部是一个多级Clos网络,每一级有相应的仲裁模块对请求进行调度,数据包缓存在输入/输出端口实现,除去这些缓冲区单元,该网络是无缓存的。最后通过BookSim模拟器进行了大量的性能测试,所设计的路由器能够正常工作,性能良好。

Design and implementation of a multi stage bufferless high radix router

As the scale of high performance networks is increasing,the design of high radix router architectures is becoming a hotspot in the field of high performance computing. Using high radix routers, the network can achieve lower transmission latency, lower cost of network construction and lower power consumption, and improve network reliability simultaneously. As the radix of high performance routers increases continuously, simply extending the radix of single stage crossbar fabric can greatly increase internal connection resources inside the routers, and the cost of switches becomes unbearable.So there is a pressing need to design a new fabric for high radix routers. Over the past decade, the structured designs represented by the YARC and the "network within a network" approach have appeared, and future study focuses on solving all kinds of problems such as buffer and arbitration to design better architectures.We implement a high radix router with a multi stage Clos network inside and there are corresponding arbitration modules to schedule requests for each stage. Packet memory buffers are implemented at input and output ports, and the network is bufferless besides these memories. We conduct extensive simulations to evaluate the performance in BookSim simulator, and the results show that the high radix router we design works properly and provides good performance.