容错处理器阵列的多逻辑列并行重构算法

处理器阵列的容错重构技术是片上网络多核、众核高性能体系结构的可靠性技术之一。现有的最大逻辑阵列并行重构技术仅对单条逻辑列的构造实现了并行化，而对多条逻辑列的同步并行仍未见可行算法。依据处理器阵列的潜在并行性，在分治策略的基础上，提出了一种阵列分块的并行重构算法。算法对处理器阵列实施横向分块划分，对每个阵列块进行并行重构，并对所得逻辑子阵列进行归并，实现了多条逻辑列的同步并行重构。与现有的并行算法相比，新算法同样能够生成最大逻辑列，并且减少了通信开销与计算中的数据冗余，有效提高了运行速度。实验结果表明，在物理阵列大小为64×64的处理器阵列上，运行速度比现有并行算法提高39.55%，并且具有良好的可扩展性。

A parallel multiple logical columns reconfiguration algorithm on fault-tolerant processor arrays

Efficient fault-tolerant reconfiguration techniques are essential for improving the reliability of high performance architecture such as mesh-connected processor arrays. Meanwhile, reconfiguration must be achieved as fast as possible to meet the real-time constraints. Existing techniques of generating maximum logic array on parallel reconfiguration are only for the single logical column, and no maximum logic array algorithm is reported for reconfiguring multi-logical columns in parallel on processor arrays. According to the potential parallelism of mesh-connected processor arrays, based on the divide and conquer strategy, this paper proposes a parallel algorithm to reconstruct the logical array. The proposed algorithm divides processors array into subarrays, then reconfigures each subarray in parallel. After that, it merges the logical subarrays in parallel. The proposed algorithm can effectively accelerate the running speed by reducing the data redundancy in communication and calculation. Moreover, it is proved that the proposed algorithm can generate the maximum logic array. Experimental results show that the proposed algorithm is faster by nearly 39.6% than the existing parallel algorithm on a 64×64 processor array and has good scalability.