| 并行自动测试系统硬件结构研究 |
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| 引用本文： | 卓家靖,孟晨,方丹.并行自动测试系统硬件结构研究[J].计算机测量与控制,2009,17(5):820-821,853. |
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| 作者姓名： | 卓家靖 孟晨 方丹 |
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| 作者单位： | 1. 军械工程学院,导弹工程系,河北,石家庄,050003;武汉军械士官学校,湖北,武汉,430075
2. 军械工程学院,导弹工程系,河北,石家庄,050003 |
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| 摘 要： | 为实现自动测试系统高效率和低成本,对并行自动测试系统的硬件结构进行了研究,提出了单处理器架构方式下的并行自动测试系统硬件结构;并具体对测试控制器、接口总线、仪器资源以及开关系统等各硬件模块的特点进行了研究,通过分析它们对并行测试的支持,明确了并行自动测试系统设计中的关键技术,可指导系统的实际开发。
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| 关 键 词： | 自动测试系统 并行测试 硬件结构 仪器资源 开关系统 |
Research on the Hardware Architecture of Parallel Auto Test System |
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| Zhuo Jiajing,Meng Chen,Fang Dan.Research on the Hardware Architecture of Parallel Auto Test System[J].Computer Measurement & Control,2009,17(5):820-821,853. |
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| Authors: | Zhuo Jiajing Meng Chen Fang Dan |
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| Affiliation: | 1 .Department of Missile Engineering;Ordnance Engineering College;Shijiazhuang 050003;China;2 .Wuhan Ordnance Noncommissioned Officer School;Wuhan 430075;China |
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| Abstract: | For the purposes of high eff iciency and low cost, the hardware architecture of parallel auto test system with single CPU is put forward. The character of the hardware modules in the system such as test controller,interface buses,instrument resources and switch system are researched in detail. And through analyzing the character in the application of parallel test, the key in the design of parallel auto test system is def ined. It can guide the development of the system. |
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| Keywords: | auto test system parallel test hardware architecture instrument resource switch system |
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