| Abstract: | Time-to-market and implementation cost are high-priority considerations in the automation of digital hardware design. Nowadays, digital signal processing applications are implemented into fixed-point architectures due to its advantage of manipulating data with lower word-length. Thus, floating-point to fixed point conversion is mandatory. This conversion is translated into optimizing the integer word length and fractional word length. Optimizing the integer word-length can significantly reduce the cost when the application is tolerant to a low probability of overflow. In this paper, a new selective simulation technique to accelerate overflow effect analysis is introduced. A new integer word-length optimization algorithm that exploits this selective simulation technique is proposed to reduce both implementation cost and optimization time. The efficiency of our proposals is illustrated through experiments, where selective simulation technique allows accelerating the execution time of up to 1200 and 1000 when applied on Global Positioning System and on Fast Fourier Transform part (FFT) of Orthogonal Frequency Division Multiplexing chain respectively. Moreover, applying the optimization algorithm on the FFT part leads to a cost reduction between 17 to 22 % with respect to interval arithmetic and an acceleration factor of up to 617 with respect to classical max-1 algorithm. |
