An efficient built-in self testing for random-access memory |
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Authors: | Mazumder P Patel JH |
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Affiliation: | Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI; |
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Abstract: | The authors propose a test algorithm for pattern-sensitive faults in large-size RAM with high circuit density. The algorithm tests an n-bit RAM in 195√n time to detect both static and dynamic pattern-sensitive faults over the 9-neighbourhood of every memory cell. A 4 Mb RAM can be tested by the proposed algorithm several thousand times faster than the conventional sequential algorithms for detecting pattern-sensitive faults. The test speedup has been achieved by writing a test data simultaneously over many cells, and the stored data are tested simultaneously by a parallel comparator and error detector in a read operation. The existing RAM architecture has been modified very little so that the proposed technique can be implemented very easily even in switched-capacitor DRAM (dynamic random-access memory) with low intercell pitch width. The test procedure has also been applied to built-in self-testing (BIST) and is compared with other BIST implementations |
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