Hole mobility enhancement in strained-Si p-MOSFETs under high vertical field |
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Authors: | Chinmay K Maiti LK Bera SS Dey DK Nayak NB Chakrabarti |
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Affiliation: | Department of Electronics & ECE, IIT, Kharagpur 721302, India |
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Abstract: | The growth of a high quality, step-graded lattice-relaxed SiGe buffer layer on a Si(100) substrate is investigated. p-MOSFETs were fabricated on strained-Si grown on top of the above layer. Carrier confinement at the type-II strained-Si/SiGe buffer interface is observed clearly from the device transconductance and C-V measurements. At high vertical field, compared to bulk silicon, the channel mobility of the strained-Si device with x=0.18 is found to be about 40% and 200% higher at 300 K and 77 K respectively. Measurements on transconductance enhancement are also reported. Data at 77 K provide evidence of two channels and a large enhancement of mobility at high transverse field. |
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