Designing the MPC105 PCI bridge/memory controller |
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| Authors: | Wang K Bryant C Carlson M Elmer T Harris A Garcia M Hui CS Leong CK Reynolds B Tang R Weber L Wenzel J Wilson G Becker M |
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| Affiliation: | Somerset Design Center, Austin, TX; |
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| Abstract: | The MPC105 peripheral component interconnection bridge/memory controller provides a platform-specification-compliant bridge between Power PC microprocessors and the PCI bus. With it, designers can create systems using peripherals already designed for a variety of standard PC interfaces. This bridge chip also integrates a secondary cache controller and high-performance memory controller that supports DRAM or synchronous DRAM and ROM or flash ROM |
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