| 静态时序分析及其在IC设计中的应用 |
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| 引用本文： | 张富彬, HO Ching-yen, 彭思龙,. 静态时序分析及其在IC设计中的应用[J]. 电子器件, 2006, 29(4): 1329-1333 |
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| 作者姓名： | 张富彬 HO Ching-yen 彭思龙 |
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| 作者单位： | 1. 中国科学院自动化研究所,国家专用集成电路设计工程研究中心,北京,100080
2. Synopsys Inc.Mountain View CA 94043 |
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| 摘 要： | 讨论了静态时序分析算法及其在IC设计中的应用。首先，文章讨论了静态时序分析中的伪路径问题以及路径敏化算法，分析了影响逻辑门和互连线延时的因素。最后通过一个完整的IC设计流程介绍了静态时序分析的应用。
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| 关 键 词： | 静态时序分析 敏化路径 伪路径 D-算法 |
| 文章编号： | 1005-9490（2006）04-1329-05 |
| 收稿时间： | 2005-12-30 |
| 修稿时间： | 2005-12-30 |
Static Timing Analysis and Its Application in IC Design |
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| ZHANG Fu-bin~,HO Ching-Yen~,PENG Si-long~. Static Timing Analysis and Its Application in IC Design[J]. Journal of Electron Devices, 2006, 29(4): 1329-1333 |
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| Authors: | ZHANG Fu-bin~ HO Ching-Yen~ PENG Si-long~ |
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| Affiliation: | 1. National ASIC Design Engineering Center, Institute of Automation, Chinese Academy of Science, Beijing 100080, China; 2. Synopsys Inc. Mountain View CA 94043 |
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| Abstract: | This paper addresses static timing analysis and its application in integrate circuits design. Firstly, false paths in static timing analysis and the algorithm to sensitize paths are presented, and then some factors affecting gates and interconnects delay are discussed. Finally, a whole integrate circuits design flow is introduced to emphasize the application of static timing analysis. |
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| Keywords: | static timing analysis sensitize paths false paths D-algorithm |
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