Fault Diagnosis in Lab-on-Chip Using Digital Microfluidic Logic Gates

Fault diagnosis is needed for a lab-on-chip to facilitate defect tolerance using reconfiguration. Previously proposed techniques for reading test outcomes and for pulse-sequence analysis are cumbersome and error-prone. We present a fault-diagnosis method to locate a single defective cell and multiple rows/columns with defective cells in a digital microfluidic array. The proposed method can also locate an unknown number of rows/columns-under-test with defective cells. It utilizes digital microfluidic exclusive-or gates to implement an output compactor. The microfluidic compactor can compress 2 ^r distinct test outcomes to a r-droplet signature. This approach obviates the need for capacitive sensing test-outcome circuits for analysis. We analyze the probability of misdiagnosis and use the compression ratio as a measure to evaluate the proposed fault-diagnosis method.