| 多级并接型权电阻DAC的设计 |
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| 引用本文： | 王振宇.多级并接型权电阻DAC的设计[J].电气电子教学学报,2002,24(6):43-45. |
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| 作者姓名： | 王振宇 |
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| 作者单位： | 解放军电子工程学院,安徽,合肥,230037 |
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| 摘 要： | 多级并接型权电阻解码网络结构简单，分析方便，文章给出了普通的和BCD码多级并接型权电阻解码网络，推导出了各级与运放的连接电阻的通用公式，并用EWB软件进行了电路模拟，这种方法对自行设计权电阻DAC有一定的参考价值。
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| 关 键 词： | DAC 并接 多级 权电阻 通用公式 |
| 文章编号： | 1008-0686(2002)06-0043-03 |
| 修稿时间： | 2002年7月28日 |
The Design and Simulation of Multi-Stage Parallel Connecting Weighted Resistor DACs |
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| WANG Zhen,yu.The Design and Simulation of Multi-Stage Parallel Connecting Weighted Resistor DACs[J].Journal of Electrical & Electronic Engineering Education,2002,24(6):43-45. |
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| Authors: | WANG Zhen yu |
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| Abstract: | Multi stage parallel connecting weighted resistor decoding network has the properties of simple structure and easy analysis. This paper gives out the weighted resistor decoding networks of normal DAC and BCD code DAC, works out the universal formulas of connecting resistors, and simulates the circuit with EWB. This method has some reference value to design weighted resistor DAC. |
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| Keywords: | parallel connecting multi stage weighted resistor universal formulas simulate |
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