| 5Gb/s 0.25μm CMOS限幅放大器 |
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| 引用本文： | 胡艳,王志功,冯军,熊明珍.5Gb/s 0.25μm CMOS限幅放大器[J].半导体学报,2003,24(12). |
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| 作者姓名： | 胡艳 王志功 冯军 熊明珍 |
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| 作者单位： | 东南大学射频与光电集成电路研究所,南京,210096 |
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| 基金项目： | 国家自然科学基金，国家高技术研究发展计划(863计划) |
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| 摘 要： | 采用TSMC 0.25μm CMOS技术设计实现了高速低功耗光纤通信用限幅放大器.该放大器采用有源电感负载技术和放大器直接耦合技术以提高增益,拓展带宽,降低功耗并保持了良好的噪声性能.电路采用3.3V单电源供电,电路增益可达50dB,输入动态范围小于5mVpp,最高工作速率可达7Gb/s,均方根抖动小于0.03UI.此外核心电路功耗小于40mW,芯片面积仅为0.70mm×0.70mm.可满足2.5,3.125和5Gb/s三个速率级的光纤通信系统的要求.
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| 关 键 词： | 限幅放大器 有源电感 并联峰化技术 CMOS |
5Gb/s 0. 25μm CMOS Limiting Amplifier |
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| Hu Yan,Wang Zhigong,Feng Jun,Xiong Mingzhen.5Gb/s 0. 25μm CMOS Limiting Amplifier[J].Chinese Journal of Semiconductors,2003,24(12). |
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| Authors: | Hu Yan Wang Zhigong Feng Jun Xiong Mingzhen |
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| Abstract: | A limiting amplifier (LA) IC implemented in TSMC standard 0. 25μm CMOS technology is described. Active inductor loads and direct-coupled technology are employed to increase the gain ,broaden the bandwidth ,reduce the power dissipation,and keep a tolerable noise performance. Under a 3.3V supply voltage ,the LA core achieves a gain of 50-dB with a power consumption below 40mW. The measured input sensitivity of the amplifier is better than 5mVpp. It can operate at bit rates up to 7Gb/s with an rms jitter of 0.03 UI or less. The chip area is only 0.70mm × 0.70mm. According to the measurement results, this IC is expected to work at the standard bit rate levels of 2.5, 3. 125, and 5Gb/s. |
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| Keywords: | limiting amplifier active inductor shunt peaking technique CMOS |
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