aDepartment of EE, University of California, Los Angeles, USA
bDepartment of Electrical and Computer Engineering, Portland State University, OR, USA
cIBM, EDA Lab, Hopewell Junction, NY 12533, USA
Abstract:
Congestion estimation is an important issue for design automation of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A probabilistic model of interconnections enables designers to quickly predict routing congestion. We propose a powerful and fast estimation approach that allows wires to have bounded-length detours to bypass congestions. The method is more realistic and precise than the previous work. The experimental results demonstrate the effectiveness of the method on routing benchmarks.